1. Field of the Invention
The present invention relates generally to solid-state imaging devices, and more particularly to a highly integrated solid-state imager including an array of picture elements or cells each having a diode for storing therein a packet of photoelectrically produced signal-charge carriers indicative of an incident image introduced from a scene.
2. Description of the Related Art
Solid-state image sensing devices are becoming more widely used in the manufacture of photoelectric equipments, including video movie cameras, electronic still cameras, input image acquisition devices for computer systems, etc., as the reliability and cost advantages of these imaging devices increase. The cost per cell of storage using solid-state imagers has gone down as the number of cells or picture element per package goes up.
A charge-coupled device (CCD) is well known as one of the solid-state image sensing devices. A presently available CCD imager is arranged to include a substrate, an array of rows and columns of picture elements or cells (called the "pixels" in the art of image sensors) on the substrate, and a charge transfer section coupled to the array of cells on the substrate. Typically, each cell includes a diode that stores or integrates therein a packet of charge carriers indicative of an input optical image. The charge transfer section includes a plurality of first parallel charge transfer sections coupled to the rows of cells. Each of these transfer sections allows the charge carriers, which are called the "signal charge" in the CCD imager art, to move together from the cells in a corresponding one of the rows and transfer sequentially toward an output of each transfer section. The first charge transfer sections are called the "vertical charge-transfer registers." The charge transfer section also includes a second charge transfer section, which may be called the "horizontal charge-transfer register." This horizontal transfer register is coupled to the outputs of the vertical transfer registers, for causing the signal charge fed thereinto by the vertical transfer registers to sequentially transfer toward its output, which may be connected to an amplifier circuitry.
As the number of cells increases, the size of them decreases, the effective photosensitive area decreases in each cell, and the magnitude of the charge-storage diode in each cell of necessity decreases. These factors reduce the sensitivity of the CCD imager as a whole. Another saying of this is that there is a trade-off between the achievement of a higher integration density and the achievement of a higher reliability: Making the cell size smaller can improve the CCD integration density, but making it too small can also degrade the reliability; the performance of photoelectric conversion (the efficiency of the generation amount of effective signal charge carriers per incident light) decreases, causing the signal-to-noise ratio to decrease.
Conventionally, a highly integrated CCD imaging device is known which attains an increased area of cells on a substrate of a limited size, by specifically arranging so that a photoconductive layer is stacked on CCD elements of vertical and horizontal charge transfer registers, thus causing the photosensitive area to increase. With such a stacked type CCD imager, since the charge-storage diode is prevented from being completely depleted in each cell, what is called a "capacitive afterimage" phenomenon will possibly take place depending upon the presence of a static capacitance of the storage diode. To eliminate the occurrence of such an afterimage, the storage diode is potentially reset, by injecting a charge into the storage diode and then causing the charge to be drained before the signal-charge storage period. However, with such a potential reset scheme for the storage diode, what is called the "fixed-pattern noise generation" problem is raised as will be described below.
The prior-art CCD imager is arranged in the individual cell as follows. A semiconductor substrate of P type conductivity has a top surface including a specific surface area surrounded by a heavily-doped P type (P+ type) semiconductive channel stopper layer, which is same in conductivity type as the substrate. Three spaced-apart N type semiconductor layers are arranged in the specific area: a heavily-doped N type (N+ type) storage-diode layer, an N type CCD register layer, and an N+ type carrier-injection diode layer that is coupled to the channel stopper layer. A transfer channel region is defined between the storage diode layer and the CCD register layer. A conductive layer acting as a transfer electrode overlies the CCD register and the transfer channel region. A gate electrode (carrier injection electrode) overlies a substrate surface area as defined between the CCD register layer and the injection diode layer. A photoconductive layer is arranged to overlie all the above components over the substrate so that this layer is connected to the storage-diode layer. The photoconductive layer is covered with a transparent electrode on its flat top surface.
When an incident light enters the photoconductive layer, this layer produces electrons and holes by the photoelectric conversion effect. The electrons are collected in the storage diode as the effective signal charge carriers. During such a charge integration or storage period, the transfer electrode is at the ground potential, causing the stored charge carriers to be prevented from being read out of the diode to the CCD register layer. At the end of the charge storage period, the transfer electrode goes high in potential, causing the signal charge to move from the diode toward the CCD register layer through the transfer channel region. This means that all the signal charge is read out of the storage diode into a corresponding one of parallel vertical transfer registers at a time. The storage diode potentially approaches the transfer channel region. If the potential difference therebetween becomes a specific value, the transfer channel region begins to exhibit relatively large resistance value. Due to the presence of such large channel resistance, a part of the signal charge is unable to flow into the CCD register layer and remain in the storage diode continuously. If such carriers are read out lately during a following field period, a resultant image may contain an afterimage component undesirably.
To eliminate the occurrence of an afterimage, the prior-art CCD imager is arranged to potentially reset the storage diode by (1) injecting an extra packet of charge carriers into the storage diode in each cell, and (2) then forcing the charge packet to drain away from the diode to the injection diode. With such a reset operation, the storage diode is rendered constant in potential at the beginning of every field period, whereby any charge indicative of a pixel image of a prior field period is no longer remained, so that no afterimage takes place.
With such a storage-diode reset scheme, while the transparent electrode is fixed at a predetermined potential of the positive polarity throughout the entire operation period, the transfer electrode varies in potential to be at different potential levels during the signal-charge read period and the reset period. More specifically, during the reset period, the transfer electrode is set at a positive-polarity potential for the injection and exhaust of extra charge carriers. During the signal-charge read period, the transfer electrode (1) potentially drops down causing the channel region to turn off to thereby allow a charge to be stored or integrated in the storage diode, and then (2) rises in potential again causing the signal charge to be read out of the storage diode toward the CCD register. The potential of the transfer electrode at this time is higher than its potential as held during the reset operation, whereby a certain amount of charge corresponding to the potential difference may be also read out as a "bias charge" in addition to the signal charge.
It will not always occur that, when the transfer electrode varies in potential as described above, each of the transfer channel regions for an increased number of cells potentially varies so as to follow it precisely. Another saying of this is that, even if the potential of the transfer electrode was set at a preselected potential level with respect to the individual cell, it cannot be expected that the potential of transfer channel region remains uniform among the cells. Practically, it is more likely that the channel-region potential may vary in potential among the cells during the operation of the CCD imager. The reason for this is that the cells may vary inevitably in the thickness of a dielectric film arranged between the substrate and the transfer electrode, the impurity doping density of channel region, the length of channel region, and the like due to the occurrence of inherent variations in the semiconductor process parameters during the manufacture of CCD imager devices. Naturally, such variations of the transfer channel potential among the cells result in that the bias charge becomes variable in amount with respect to respective cells. The bias charge variation causes a fixed-pattern noise generation" problem to take place undesirably. The signal-to-noise ratio is thus reduced causing a reproduced image to decrease in quality.
A stacked type solid-state imaging device is disclosed, for example, in U.S. Pat. No. 4,912,560 granted Mar. 27, 1990 under the title of "Solid State Image Sensing Device" (Assignee is Kabushiki Kaisha Toshiba), wherein the imager has a photoconductive film stacked to overlie an array of cells. Each of these cells includes an N type storage diode layer, which is arranged in a P type well region formed in the surface of an N type semiconductor substrate. A vertical CCD register is also arranged in the well region to define a channel between the storage-diode layer and itself. A transfer electrode overlies the channel to act as an insulated gate of a resultant metal oxide semiconductor (MOS) transistor structure. The storage diode is reset by injecting charge and then draining it away in such a manner that excessive bias charges are discharged by way of the vertical CCD register by forcing the gate to go high.